A new dynamic random access memory cell using a bipolar MOS composite structureCHUNG-YU WU.I.E.E.E. transactions on electron devices. 1983, Vol 30, Num 8, pp 886-894, issn 0018-9383Article

Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC'sMING-DOU KER; CHUNG-YU WU.I.E.E.E. transactions on electron devices. 1995, Vol 42, Num 7, pp 1297-1304, issn 0018-9383Article

Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I: theoretical derivationMING-DOU KER; CHUNG-YU WU.I.E.E.E. transactions on electron devices. 1995, Vol 42, Num 6, pp 1141-1148, issn 0018-9383Article

Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II: quantitative evaluationMING-DOU KER; CHUNG-YU WU.I.E.E.E. transactions on electron devices. 1995, Vol 42, Num 6, pp 1149-1155, issn 0018-9383Article

Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS invertersCHUNG-YU WU; MING-CHUEN SHIAU.IEEE journal of solid-state circuits. 1990, Vol 25, Num 5, pp 1247-1256, issn 0018-9200, 10 p.Article

Physical timing models and design methodology of bipolar nonthreshold logic circuitsCHUNG-YU WU; TAIN-SHUN WU.Solid-state electronics. 1990, Vol 33, Num 12, pp 1615-1627, issn 0038-1101, 13 p.Article

A new lateral growth free formation technique for titanium silicide using the Si/W/Ti trilayer structureMING-ZEN LIN; CHUNG-YU WU.Journal of the Electrochemical Society. 1988, Vol 135, Num 9, pp 2342-2347, issn 0013-4651Article

A new criterion for transient latchup analysis in bulk CMOSYEU-HAW YANG; CHUNG-YU WU.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 7, pp 1336-1347, issn 0018-9383, 12 p.Article

A new structure of the 2-D silicon retinaCHUNG-YU WU; CHIN-FONG CHIU.IEEE journal of solid-state circuits. 1995, Vol 30, Num 8, pp 890-897, issn 0018-9200Article

Latched CMOS differential logic (LCDL) for complex high-speed VLSICHUNG-YU-WU; KUO-HSING CHENG.IEEE journal of solid-state circuits. 1991, Vol 26, Num 9, pp 1324-1328, issn 0018-9200Article

Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applicationsCHUNG-YU WU; MING-CHUEN SHIAU; LM et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1990, Vol 9, Num 9, pp 1002-1009, issn 0278-0070Article

Physical timing models of small-geometry CMOS inverters and multi-input NAND/NOR gates and their applicationsCHUNG-YU WU; JEN-SHENG HWANG.Solid-state electronics. 1989, Vol 32, Num 6, pp 449-467, issn 0038-1101Article

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltageMING-DOU KER; CHUNG-YU WU.Solid-state electronics. 1994, Vol 37, Num 1, pp 17-26, issn 0038-1101Article

Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logicCHUNG-YU WU; HONG-YI HUANG.IEEE journal of solid-state circuits. 1993, Vol 28, Num 8, pp 895-906, issn 0018-9200Article

New physical timing models of bipolar nonsaturation logic using current-domain analysis techniqueCHUNG-YU WU; TAIN SHUN WU.Solid-state electronics. 1991, Vol 34, Num 4, pp 351-365, issn 0038-1101, 15 p.Article

The signal delay in interconnection lines considering the effects of small-geometry CMOS invertersMING-CHUEN SHIAU; CHUNG-YU WU.IEEE transactions on circuits and systems. 1990, Vol 37, Num 3, pp 420-425, issn 0098-4094, 6 p.Article

Physical timing models of small-geometry CMOS inverters and multi-input NAND/NOR gates and their applicationsCHUNG-YU WU; JEN-SHENG HWANG.Solid-state electronics. 1989, Vol 32, Num 6, pp 449-467, issn 0038-1101Article

THE NEW GENERAL REALIZATION THEORY OF FET-LIKE INTEGRATED VOLTAGE-CONTROLLED NEGATIVE DIFFERENTIAL RESISTANCE DEVICESCHUNG YU WU; CHING YUAN WU.1981; IEEE TRANS. CIRCUITS SYST.; ISSN 0098-4094; USA; DA. 1981; VOL. 28; NO 5; PP. 382-390; BIBL. 11 REF.Article

CHARACTERISATIONS AND DESIGN CONSIDERATIONS OF LAMBDA BIPOLAR TRANSISTOR (LBT)CHUNG YU WU; CHING YUAN WU.1981; IEE PROC., PART 1; ISSN 0143-7100; GBR; DA. 1981; VOL. 128; NO 3; PP. 73-80; BIBL. 7 REF.Article

THE EFFECT OF THE MINORITY CARRIER DISTRIBUTION ON THE THRESHOLD VOLTAGE OF A MOSFETCHUNG YU WU; HWEY CHING CHIEN.1983; SOLID-STATE ELECTRONICS; ISSN 0038-1101; GBR; DA. 1983; VOL. 26; NO 5; PP. 371-381; BIBL. 8 REF.Article

Realizations of high-order switched-capacitor filters using multiplexing techniqueCHUNG-YU WU; JENN-CHYOU BOR; BOR-SHENN JENG et al.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1994, Vol 41, Num 12, pp 778-785, issn 1057-7130Article

MOS device parameter optimization based on transient trajectory considerationsCHUNG-YU WU; WEN-HYEUH JANG; ING-DAR LIU et al.Solid-state electronics. 1990, Vol 33, Num 5, pp 489-495, issn 0038-1101, 7 p.Article

A new method for determining the terminal series resistances and high-injection coefficient of bipolar transistors in CMOS integrated circuits for computer-aided circuit modelingYEU-HAW YANG; CHUNG-YU WU; WEN-YANG CHEN et al.Solid-state electronics. 1988, Vol 31, Num 5, pp 929-936, issn 0038-1101Article

The analysis and design of CMOS multidrain logic and stacked multidrain logicCHUNG-YU WU; JINN-SHYAN WANG; MING-KAI TSAI et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 1, pp 47-56, issn 0018-9200Article

Analysis and design of a new race-free four-phase CMOS logicCHUNG-YU WU; KUO-HSING CHENG; JINN-SHYAN WANG et al.IEEE journal of solid-state circuits. 1993, Vol 28, Num 1, pp 18-25, issn 0018-9200Article